Lead C++ Software Engineer - Palladium Emulation Platform
Cadence Design Systems
About the role
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
The Cadence Palladium Platform is world most scalable emulation system that verifies most of the latest design innovations in electronics worldwide. We are looking for a talented engineer to join our team and contribute to the world’s fastest emulator compiler development. You’ll have a great opportunity to make a difference by applying your creativity and problem-solving skills, learn and/or apply multi-threading/distributed computing to solve large scale compile problems such logic optimization, partitioning and scheduling.
The job is located in the heart of Silicon Valley, San Jose, CA.
Strong understanding of software data structure and algorithms and proficiency in C/C++ are basic job requirements.
Requirements
MS. With 2 year experience or Ph.D in engineering, computer science or related field.
Strong understanding of data structures, algorithms and databases.
Demonstrated proficiency in C++, gdb debugging, and general software development skills
Familiarity with Linux/Unix development.
Exposure to build and version-control systems.
Coursework in Hardware Descript Language, such as Verilog, SystemVerilog, VHDL.
Exposure to electronic design platforms.
The annual salary range for California is $119,000 to $221,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
We’re doing work that matters. Help us solve what others can’t.
Responsibilities
- Contribute to development of the Palladium emulator compiler.
- Apply creativity and problem-solving to large-scale compile challenges such as logic optimization, partitioning, and scheduling.
- Learn or apply multithreading and distributed computing.
Qualifications
- MS with 2 years of experience, or a PhD, in engineering, computer science, or a related field.
- Strong understanding of data structures, algorithms, and databases.
- Proficiency in C++, gdb debugging, and general software development.
- Familiarity with Linux or Unix development.
- Exposure to build and version-control systems.
- Coursework in hardware description languages such as Verilog, SystemVerilog, or VHDL.
- Exposure to electronic design platforms.
Benefits
- Paid vacation and holidays
- 401(k) plan with employer match
- Employee stock purchase plan
- Medical, dental, and vision plan options
- Potential bonus and equity compensation
Skills mentioned
About Cadence Design Systems
Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems. Our design solutions, based on Cadence’s Intelligent System Design™ strategy, are essential for the world’s leading semiconductor and systems companies to build their next-generation products from chips to full electromechanical systems that serve a wide range of markets, including hyperscale computing, mobile communications, automotive, aerospace, industrial, life sciences and robotics. In 2024, Cadence was recognized by the Wall Street Journal as one of the world’s top 100 best-managed companies. Cadence solutions offer limitless opportunities—learn more at www.cadence.com.
H-1B sponsorship history
Historical employer filing data was found for Cadence Design Systems. The employer record includes 1,739 historical certified applications. This is employer-level history, not a guarantee that this role currently offers sponsorship.